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Freescale Semiconductor /MK24F12 /FTM2 /SYNCONF

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Interpret as SYNCONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)HWTRIGMODE 0 (0)CNTINC 0 (0)INVC 0 (0)SWOC 0 (0)SYNCMODE 0 (0)SWRSTCNT 0 (0)SWWRBUF 0 (0)SWOM 0 (0)SWINVC 0 (0)SWSOC 0 (0)HWRSTCNT 0 (0)HWWRBUF 0 (0)HWOM 0 (0)HWINVC 0 (0)HWSOC

SYNCMODE=0, SWWRBUF=0, SWRSTCNT=0, SWOC=0, HWINVC=0, HWTRIGMODE=0, HWWRBUF=0, HWOM=0, HWRSTCNT=0, SWINVC=0, SWOM=0, INVC=0, CNTINC=0, HWSOC=0, SWSOC=0

Description

Synchronization Configuration

Fields

HWTRIGMODE

Hardware Trigger Mode

0 (0): FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.

1 (1): FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
CNTINC

CNTIN Register Synchronization

0 (0): CNTIN register is updated with its buffer value at all rising edges of system clock.

1 (1): CNTIN register is updated with its buffer value by the PWM synchronization.
INVC

INVCTRL Register Synchronization

0 (0): INVCTRL register is updated with its buffer value at all rising edges of system clock.

1 (1): INVCTRL register is updated with its buffer value by the PWM synchronization.
SWOC

SWOCTRL Register Synchronization

0 (0): SWOCTRL register is updated with its buffer value at all rising edges of system clock.

1 (1): SWOCTRL register is updated with its buffer value by the PWM synchronization.
SYNCMODE

Synchronization Mode

0 (0): Legacy PWM synchronization is selected.

1 (1): Enhanced PWM synchronization is selected.
SWRSTCNT

FTM counter synchronization is activated by the software trigger.

0 (0): The software trigger does not activate the FTM counter synchronization.

1 (1): The software trigger activates the FTM counter synchronization.
SWWRBUF

MOD, CNTIN, and CV registers synchronization is activated by the software trigger.

0 (0): The software trigger does not activate MOD, CNTIN, and CV registers synchronization.

1 (1): The software trigger activates MOD, CNTIN, and CV registers synchronization.
SWOM

Output mask synchronization is activated by the software trigger.

0 (0): The software trigger does not activate the OUTMASK register synchronization.

1 (1): The software trigger activates the OUTMASK register synchronization.
SWINVC

Inverting control synchronization is activated by the software trigger.

0 (0): The software trigger does not activate the INVCTRL register synchronization.

1 (1): The software trigger activates the INVCTRL register synchronization.
SWSOC

Software output control synchronization is activated by the software trigger.

0 (0): The software trigger does not activate the SWOCTRL register synchronization.

1 (1): The software trigger activates the SWOCTRL register synchronization.
HWRSTCNT

FTM counter synchronization is activated by a hardware trigger.

0 (0): A hardware trigger does not activate the FTM counter synchronization.

1 (1): A hardware trigger activates the FTM counter synchronization.
HWWRBUF

MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.

0 (0): A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.

1 (1): A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
HWOM

Output mask synchronization is activated by a hardware trigger.

0 (0): A hardware trigger does not activate the OUTMASK register synchronization.

1 (1): A hardware trigger activates the OUTMASK register synchronization.
HWINVC

Inverting control synchronization is activated by a hardware trigger.

0 (0): A hardware trigger does not activate the INVCTRL register synchronization.

1 (1): A hardware trigger activates the INVCTRL register synchronization.
HWSOC

Software output control synchronization is activated by a hardware trigger.

0 (0): A hardware trigger does not activate the SWOCTRL register synchronization.

1 (1): A hardware trigger activates the SWOCTRL register synchronization.

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data